For standard two-port SRAMs with simultaneous read and write capability, two more pass transistors and an extra pair of bit lines in addition to the conventional 6T SRAM memory cell are needed. Techniques with single-bit-line read and write have been studied for reducing the size of the two-port SRAM memory cell [K. Sasaki, et al, "A 16-Mb CMOS SRAM with a 2.3 um.sup.2 Single-Bit-Line Memory Cell," IEEE J. Solid St. Ckts, Vol. 28, pp. 1125-1130, November 1993]. However, for the 6T SRAM memory cell with the single-bit-line write structure, write logic-1 operation via the single bit line is difficult due to the ratioed logic structure involved. This problem is especially serious for the lowvoltage environment. Recently, SOI CMOS dynamic threshold technique has been reported for its advantages in low-voltage logic circuits [J. B. Kuo and K. W. Su, "CMOS VLSI Engineering: Silicon-on-Insulator (SOI)," Kluwer: Dordrecht, 1998.; F. Assaderaghi, et al, "A Dynamic Threshold voltage MOSFET (DTMOS) for Very Low Voltage Operation," IEEE Elec. Dev. Let., Vol. 15, pp. 510-512, December 1994].